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LD7577JA 8/16/2010 1 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 high voltage green-mode pwm controller with brown-out protection rev. 00b general description the LD7577JA integrated several functions of protections, and emi-improved solution in a sop-7, sop-8/or dip-8 package. it minimizes the component counts and the circuit space, and it?s perfect for the low cost of applications. it provides functions of low startup current, green-mode power-saving operation, lead ing-edge blanking of the current sensing and internal slope compensation. also, the LD7577JA features more protections like olp (over load protection), ovp (ove r voltage protection), and brownout protection to prevent the circuit being damaged from the abnormal conditions. furthermore, the LD7577JA feat ures frequency trembling to suppress the noise and is an excellent solution for emi filter design. features z high-voltage (500v) startup circuit z current mode control z non-audible-noise green mode control z uvlo (under voltage lockout) z leb (leading-edge blanking) on cs pin z internal frequency trembling z internal slope compensation z internal over current compensation z ovp (over voltage protection) on vcc z ac input ovp (over voltage protection) z olp (over load protection) z brownout protection z 500ma driving capability applications z switching ac/dc adaptor and battery charger z open frame switching power supply z lcd monitor/tv power typical application emi filter photocoupler ac input tl431 * * *see application information LD7577JA vcc hv bno gnd comp cs out free datasheet http:///
LD7577JA 2 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 pin configuration yy: year code ww: week code pp: production code sop-8 & dip-8 (top view) 1 8 2 3 4 7 6 5 top mark yywwpp bno comp cs gnd hv nc vcc out sop-7 (top view) 1 8 2 3 4 6 5 to p mark yywwpp bno comp cs gnd hv vcc out ordering information part number switching freq. package top mark shipping LD7577JA gr 65khz sop-7 LD7577JAgs 2500 /tape & reel LD7577JA gs 65khz sop-8 LD7577JAgs 2500 /tape & reel LD7577JA gn 65khz dip-8 LD7577JAgn 3600 /tube /carton note: the LD7577JA is green packaged. pin descriptions sop-8 dip-8 sop-7 name function 1 1 bno brownout protection pin. connect a resi stor divider between this pin and bulk capacitor voltage to set the brow nout level. if the voltage is below threshold voltage, the pwm output will be disabled. the bno pin also provides ac over voltage protection. as soon as the voltage is over 4.16v, the ovp will be tripped and t he gate drive will be turned off. 2 2 comp voltage feedback pin. through the conn ection of a photo-coupler, it can close the control loop and achieve the regulation. 3 3 cs current sense pin. connect it to sense the mosfet current. 4 4 gnd ground. 5 5 out gate drive output to drive the external mosfet. 6 6 vcc supply voltage pin. 7 --- nc unconnected pin. 8 8 hv connect this pin to positive terminal of bulk capacitor to provide the startup current for the controller. when vcc vo ltage trips uvlo(on), this hv loop will be turned off to save the power loss of the startup circuit. free datasheet http:///
LD7577JA 3 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 block diagram free datasheet http:///
LD7577JA 4 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 absolute maximum ratings supply voltage vcc -0.3v~30v high-voltage pin, hv -0.3v~500v comp, bno, cs -0.3v ~7v out -0.3v ~vcc+0.3v maximum junction temperature 150 c operating ambient temperature range -40 c to 85 c operating junction temperature range -40 c to 125 c storage temperature range -65 c to 150 c package thermal resistance (sop-7, sop-8) 160 c/w package thermal resistance (dip-8) 100 c/w power dissipation (sop-7, sop-8, at ambient temperature = 85 c) 400mw power dissipation (dip-8, at ambient temperature = 85 c) 650mw lead temperature (soldering, 10sec) 260 c esd voltage protection, human body model (except hv pin) 2.5kv esd voltage protection, machine model 250v gate output current 500ma caution: stresses beyond the ratings specified in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above t hose indicated in the operational sections of this s pecification is not implied. free datasheet http:///
LD7577JA 5 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 electrical characteristics (t a = +25 c unless otherwise stated, v cc =15.0v) parameter conditions min typ max units high-voltage supply (hv pin) high-voltage current source v cc < uvlo(on), hv=500v 0.5 1.0 1.5 ma off-state leakage current v cc > uvlo(off), hv=500v 35 a supply voltage (vcc pin) startup current 320 a v comp =0v,fsw=65khz 3.3 ma v comp =3v,fsw=65khz 3.6 ma olp tripped 0.78 ma operating current (with 1nf load on out pin) ovp tripped 0.88 ma uvlo (off) 9.0 10.0 11.0 v uvlo (on) 15.0 16.0 17.0 v ovp level 26.5 28.0 29.5 v voltage feedback (comp pin) short circuit current v comp =0v 1.5 2.2 ma open loop voltage comp pin open 5.8 v green mode threshold vcomp 2.35 v burst mode threshold vcomp 1.4 v current sensing (cs pin) maximum input voltage(vcs_off) 0.80 0.85 0.90 v comp >1.9v 320 ns leading edge blanking time comp <1.9v 750 ns input impedance 1 m delay to output 100 ns oscillator for switching frequency frequency f sw =65khz 60 65 70 khz trembling frequency 4 khz green mode frequency f sw =65khz 22 khz modulation frequency f sw =65khz 86 hz temp. stability 5 % voltage stability vcc=11v-25v 1 % free datasheet http:///
LD7577JA 6 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 brownout protection & line compensation (bno pin) brownout turn-on trip level 1.00 1.05 1.10 v brownout turn-off trip level 0.90 0.95 1.00 v line voltage ovp-off lev el 4.06 4.16 4.26 v line voltage ovp-on level 3.82 3.92 4.02 v saturation voltage on bno pin ibno=1.5 a 6.0 v gate drive output (out pin) output low level vcc=15v, io=20ma 1 v output high level vcc=15v, io=20ma 9 v rising time load capacitance=1000pf 100 160 ns falling time load capacitance=1000pf 30 60 ns olp (over load protection) olp trip level 5.0 v olp delay time fsw=65khz 30 ms de_latch vcc level pdr (power down reset) 8.0 v free datasheet http:///
LD7577JA 7 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 typical performance characteristics hv current source (ma) temperature ( c) fig. 1 hv current source vs. temperature (hv=500v, vcc=0v) 0.7 0.9 1.1 1.3 1.5 -40 0 40 80 120 125 v cs (off) (v) temperature ( c) fig. 2 v cs (off) vs. temperature 0.85 0.86 0.87 0.88 0.89 0.90 -40 0 40 80 120 125 uvlo (on) (v) fig. 3 uvlo (on) vs. temperature temperature ( c) 14.0 14.8 15.6 16.4 17.2 18.0 -40 0 40 80 120 125 uvlo (off) (v) temperature ( c) fig. 4 uvlo (off ) vs. temperature 8 9.6 10.4 12 8.8 -40 0 40 80 120 125 11.2 frequency (khz) fig. 5 frequency vs. temperature temperature ( c) -40 60 62 64 66 68 70 0 40 80 120 125 frequency (khz) temperature ( c) fig. 6 green mode frequency vs. temperature 16 18 20 22 24 26 -40 0 40 80 120 125 free datasheet http:///
LD7577JA 8 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 frequency (khz) vcc (v) fig. 7 frequency vs. vcc 12 14 16 18 20 22 24 60 11 25 62 64 66 68 70 green mode frequency (khz) vcc (v) fig. 8 green mode frequency vs. vcc 12 14 16 18 20 22 24 11 25 19 21 23 25 17 15 max duty (%) temperature ( c) fig. 9 max duty vs. temperature -40 0 40 80 120 125 65 70 75 80 85 60 vcc ovp (v) temperature ( c) fig. 10 vcc ovp vs. temperature 10 15 20 25 30 35 -40 0 40 80 120 125 v comp (v) temperature ( c) fig. 11 v comp open loop voltage vs. temperature -40 0 40 80 120 125 4.5 5.0 5.5 6.0 6.5 7.0 olp (v) temperature ( c) fig. 12 olp-trip level vs. temperature -40 0 40 80 120 125 3.5 4.0 4.5 5.0 5.5 6.0 free datasheet http:///
LD7577JA 9 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 i bno ( a) v bno (v) fi g. 13 v bno vs. i bno 0 0.2 0.4 0.6 0.8 1.2 1.4 1.6 0 1 2 3 4 5 6 1.0 25 c application information operation overview as long as the green power requirement becomes a trend and the power saving is becoming more and more important for switching power supplies and switching adaptors, the traditional pwm c ontrollers are not able to support such new requirements. furthermore, the cost and size limitation forces the pwm controllers to powerfully integrate more functions, thereby reducing the external part count. the LD7577JA is ideal for these applications to provide an easy and cost effective solution; and its detailed features are described as below. internal high-voltage startup circuit and under voltage lockout (uvlo) r1 out cs vcc gnd LD7577JA c1 cbulk d1 rs comp vin hv fig. 14 traditional circuits? power on the pwm controller through a startup resistor to consta ntly provide current from a rectified voltage to the capac itor connected to vcc pin. nevertheless, this startup resi stor was usually of larger resistance, and it therefor e required more power and more time to start up. to achieve the optimized topology, as shown in figure 14, the LD7577JA is built in with high voltage startup circuit to optimize the power saving. during the startup sequence, a high-voltage current source sinks current from c bulk capacitor to provide the star tup current as well as to charge the vcc capacitor c1. during the initialization of the startup, vcc voltage is lower than the uvlo(off) threshold thus the current source is on to supply a current of 1ma. meanwhile, the vcc current consumed by the LD7577JA is as low as 320 a thus most of the hv current is utilized to charge the v cc capacitor. by using such configuration, the turn-on del ay time will be almost the same no matter whether opera tion condition is under low-line or high-line. when vcc voltage reaches uv lo(on) threshold, the LD7577JA is powered on to start issuing the gate drive signal, the high-voltage current source is then disabled, and the vcc supply current will be only provided from the free datasheet http:///
LD7577JA 10 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 auxiliary winding of the trans former. therefore, the power losses on the startup ci rcuit beyond the startup period can be eliminated and the power saving can be easily achieved. in general application, a 39k ? resistor is still recommended to be placed in high voltage path to limit the current if there is a negative voltage applying in any case. an uvlo comparator is incl uded to detect the voltage on the v cc pin to ensure the supply voltage is high enough to power on the LD7577JA pwm controller and in addition to drive the power mosfet. as shown in fig. 15, a hysteresis is provided to pr event the shutdown caused by the voltage dip during startup. the turn-on and turn-off threshold levels are set at 16v and 10.0v, respectively. vcc uvlo(on) uvlo(off) t t hv current 1ma startup current vcc current ~ 0ma (off) operating current (supply from auxiliary winding) fig. 15 current sensing, leading-edge blanking and the negative spike on cs pin the typical current mode pwm controller feeds back both current signal and voltage signal to close the control loop and to achieve voltage regulation. LD7577JA detects the primary mosfet current from the cs pin, which is applied not only for the peak cu rrent mode control but also for the pulse-by-pulse current limit. the maximum voltage threshold of the current sensing pin is set as 0.85v. thus the mosfet peak current can be calculated as: s ) max ( peak r v 85 . 0 i = a 250ns leading-edge blanking (leb) time is incorporated in the input of cs pin to pr event the false-trigger caused by any current spike. for low power applications, if the total pulse width of each turn-on spike is less than 250ns and the negative spike on the cs pin is not as low as -0.3v, the r-c filter (as shown in fig.16) can be eliminated. nevertheless, it is strongly recommended to remain a small r-c filter (as shown in fig. 17) for higher power applications to avoid the cs pin being damaged by negative turn-on spikes. output stage and maximum duty-cycle an output stage of a cmos buffer, with typical 500ma driving capability, is incorporated to drive a power mosfet directly. and the maximum duty-cycle of the LD7577JA is limited to 75% in order to avoid the transformer flux saturation. voltage feedback loop the voltage feedback signal is issued from the tl431 in the secondary side through the photo-coupler to comp pin of the LD7577JA. the input stage of the LD7577JA, like the uc384x, is incorpor ated with 2 diodes voltage offset circuit and a voltage divider with 1/3 ratio. therefore, ) v 2 v ( 3 1 ) v f comp pwm ( comparator ? = + a pull-high resistor is embedded internally, eliminating external corresponding components on a board. free datasheet http:///
LD7577JA 11 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 cs vcc gnd LD7577JA can be removed if the negative spike is not over spec. (-0.3v). out 250ns blanking time fig. 16 fig. 17 oscillator and switching frequency the switching frequency of the LD7577JA is fixed as 65khz internally to provide the optimized operations by considering the emi performance, thermal treatment, component sizes and transformer design. frequency trembling the LD7577JA is implemented an adjustable frequency trembling function which provides the power supply designers to choose the optimized emi performance and lowest system cost. the trembling frequency is fixed internally 4khz which is incorporated with the 65khz switching frequency. internal slope compensation stability is crucial for current mode control when it operates at more than 50% of duty-cycle. to stabilize the control loop, the slope com pensation is required in the traditional uc384x design by injecting the ramp signal from the rt/ct pin through a coupling capacitor. in the LD7577JA, the internal slope compensation circuit has been implemented to simplify the external circuit design. on/off control pulling comp pin below 1.2v will turn off the LD7577JA and disable the gate output pin of the LD7577JA. the off-mode will be released when the pull-low signal at comp pin is removed. dual-oscillator green-mode operation lots of topologies have been implemented in different chips for the green-mode or power saving requirements such as ?burst-mode control?, ?skipping-cycle mode?, ?variable off-time control ??etc. the basic operation theory of all these approaches intends to reduce the switching cycles under light -load or no-load condition either by skipping some switching pulses or by reducing the switching frequency. free datasheet http:///
LD7577JA 12 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 what the LD7577JA uses to implement the power-saving operation is leadtrend technology?s own ip. by using this dual-oscillator control, t he burst -mode frequency can be well controlled and further to avoid the generation of audible noise. over load protection (olp) to protect the circuit from being damaged under over load condition or short condition, a smart olp function is built in with the LD7577JA, as shown in figure 18 shows the waveforms of the olp operati on. if output voltage drops, the feedback system tends to force the voltage loop toward the saturation (5.8v) and then pulls the voltage of comp pin to high. whenever the v comp trips to the olp threshold 5.0v and continues over 30ms, olp is activated and then turns off the gate output to stop the switching of power circuit. the 30ms delay time is to prevent the false trigger from the power-on and turn-off transient. a divide-2 counter is implemented to reduce the input average power through olp behavior. whenever olp is activated, the output is latched off and the divide-2 counter starts to count the number of uvlo(off). the latch is released if the 2nd uvlo(off) point is counted then the power circuit is recovered to switch again. by using such protection me chanism, the average input power can be reduced to a very low level so that the component temperature an d stress can be controlled within the safe operating area. vcc uvlo(on) uvlo(off) t t comp olp 5.0v t out olp delay time switching switching non-switching olp trip level 2nd uvlo(off) olp counter reset fig. 18 ovp (over voltage protection) on vcc the v gs ratings of the nowadays power mosfets are mostly with 30v maximum. to prevent the v gs from fault condition, the LD7577JA is implemented with over-voltage protection on vcc. as long as the vcc voltage is higher than ovp threshold voltage, the output gate drive circuit will be shut down, thus to st op the switching of the power mosfet until the next uvlo( on ). the vcc ovp function in the LD7577JA is an auto-recovery type protection. if the ovp condition, usually caused by the feedback loop opened, is not released, the vcc will trip to the ovp level again, re-shutting down the output. the vcc waveform in fig. 19 shows this auto-recovery type protection, presenting a hiccup mode. on the other hand, the remo val of the ovp condition should render the vcc level back to normal level, causing the output automatically returning to the normal operation. free datasheet http:///
LD7577JA 13 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 vcc uvlo(on) uvlo(off) t ovp tripped t out switching switching non-switching ovp level fig. 19 brownout protection & line voltage ovp (over voltage protection) the LD7577JA is programmable to set the brownout protection point and the li ne voltage ovp point though bno pin. the voltage across the bno pin is proportional to the bulk capacitor voltage, referred as the line voltage. a brownout comparator is implemented to detect the abnormal line condition. as soon as the condition is detected, it will shut down the controller to prevent the damage. figure 20 shows the operation. when v bno falls below 0.95v, the gate ou tput will be kept off even vcc has already achieved uvlo( on ). it therefore makes vcc hiccup between uvlo( on ) and uvlo( off ). unless the line voltage is large enough to pull v bno larger than 1.05v, the gate output will not start sw itching even when the next uvlo( on ) is tripped. a hysteresis is implemented to prevent the false trigger duri ng turn-on and turn-off. the comparator built in bno will disable switching from gate-out as soon as it detects excessive high line voltage and bno voltage over 4.16v. vcc will then operate in hiccup mode between uvlo -on and uvlo-off. the gate-out will not resume switching until vbno falls below 3.92v. therefore, it can pr event excessive high line voltage from damaging the external components. fig. 21 shows the operation. in order to protect bno pin from being damaged during the dividing resistors floating, an internal zener diode is implemented in bno pin. fig. 13 shows the sinking capability of the zener diod e. to protect bno pin, the current flowing in bno pin must be below 1.5 a, as shown in fig. 13. 1.05v t vcc t out switching non-switching t v bno t line voltage 0.95v non- switching ac ok area uvlo(on) uvlo(off) fig. 20 free datasheet http:///
LD7577JA 14 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 4.16 3.92 1.05v switching non- switching switching uvlo - on uvlo- off v bno line voltage vcc out t t t t ac ok area ac ok area fig.21 pull-low resistor on the gate pin of mosfet an anti-floating resistor is implemented in the out pin to prevent any uncertain output, which may cause mosfet to work abnormally or false trigger on. however, such design may not apply in all the disconnection of gate resistor r g . it is still strongly recommended to have a resistor connected at t he mosfet gate terminal (as shown in figure 22) to provide extra protection in fault conditions. this external pull-low resistor is to prevent the mosfet from being damaged during power-on when the gate resistor is disconnected. in such single-fault condition, as shown in figure 23, the resistor r8 can provide a discharge path to avoid the mosfet from being false-triggered by the couplin g through the gate-to-drain capacitor c gd . therefore, the mosfet gate should be pulled low to maintain in a off-state no matter the gate resistor is disconnected or opened in any case. fig. 22 d t dv cgd i bulk ? = fig. 23 free datasheet http:///
LD7577JA 15 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 protection resistor on the hi-v path in some other hi-v processes and designs, there is probably some parasitic scr caused around hv pin, v cc and gnd. as shown in figure 24, a small negative spike in the hv pin may trigger this parasitic scr and cause the latchup between v cc and gnd. such latchup will damage the chip easily because of the equivalent short-circuit induced. the LD7577JA has eliminated the parasitic scr efficiently. figure 25 shows the equivalent circuit of the LD7577JA?s hi-v structure. it illustrates the LD7577JA is capable to sustain negative voltage and superior than similar products. even though, a 40k resistor is still recommended to be placed on the hi-v path. fig. 24 fig. 25 free datasheet http:///
LD7577JA 16 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 reference application circu it --- 10w (5v/2a) adapter pin < 0.15w when pout = 0w & vin = 264vac photocoupler ic1 r7 q1 rs2 ic2 cy1 c5 LD7577JA bno vcc gnd comp cs out ac input f1 ntc1 cx1 r1a r1b d1a~d1d c1 r6 d4 r4a c4 t1 cr51 c51 r51a l51 c52 r51b c54 fl1 r4b zd51 r56a r56b r54 r52 c55 r55 r53 ic5 z1 4 2 1 3 8 5 d2 c2 6 hv rs1 n l r8 r9 schematic r2 r3 c3 c6 d3 free datasheet http:///
LD7577JA 17 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 package information sop-7 dimensions in millimeters dimensions in inch symbols min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.178 0.229 0.007 0.009 i 0.102 0.254 0.004 0.010 j 5.791 6.198 0.228 0.244 m 0.406 1.270 0.016 0.050 0 8 0 8 free datasheet http:///
LD7577JA 18 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 sop-8 dimensions in millimeters dimensions in inch symbols min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.178 0.229 0.007 0.009 i 0.102 0.254 0.004 0.010 j 5.791 6.198 0.228 0.244 m 0.406 1.270 0.016 0.050 0 8 0 8 free datasheet http:///
LD7577JA 19 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 package information dip-8 dimension in millimeters dimensions in inches symbol min max min max a 9.017 10.160 0.355 0.400 b 6.096 7.112 0.240 0.280 c ----- 5.334 ------ 0.210 d 0.356 0.584 0.014 0.023 e 1.143 1.778 0.045 0.070 f 2.337 2.743 0.092 0.108 i 2.921 3.556 0.115 0.140 j 7.366 8.255 0.29 0.325 l 0.381 ------ 0.015 -------- important notice leadtrend technology corp. reserves the right to make changes or corrections to its products at any time without notice. custom ers should verify the datasheets are current and complete before placing order. free datasheet http:///
LD7577JA 20 leadtrend technology corporation www.leadtrend.com.tw LD7577JA-ds-00b august 2010 revision history rev. date change notice 00 5/4/2009 original specification 00a 7/27/2009 esd voltage protection, hu man body model (except hv pin) 2.5kv leading edge blanking time update 00b 11/26/2009 1. package option: sop-7 2. top mark information free datasheet http:///

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